Data-Transfer-Aware Memory Allocation for Dynamically Reconfigurable Accelerators in Heterogeneous Multicore Processors

Accelerator cores in low-power heterogeneous multicore processors have multiple memory modules to enable parallel data access. Recent low-power processors contain address generation units (AGUs) for fast address generation. To reduce the core-area, small functional units such as adders and counters are used in AGUs. Such small functional units make it difficult to implement complex addressing patterns without duplicating the data among multiple memory modules. The data-duplication wastes the memory capacity and increases the data transfer time significantly. This paper proposes a method to remove the memory duplication and to increase the degree of parallelism. To verify the effectiveness of this method, we use window-based media processing which is widely used in many applications. According to the evaluation, the proposed method reduces the total processing time by 14% to more than 85% compared to the previous works.